Techniques for mapping device addresses to physical memory addresses

ABSTRACT

A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component interconnect (PCI) device coupled to the IOMMU, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage. The mapper is configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space. The IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.

PRIORITY CLAIM AND RELATED APPLICATION

This application is a continuation of and claims priority from U.S.patent application Ser. No. 13/452,860 filed Apr. 21, 2012, which claimspriority to European Patent Application No. EP11163339, entitled“IT-SYSTEM WITH EXTENDED IOMMU TRANSLATION FOR SIMPLIFIED I/O DEVICES,”filed Apr. 21, 2011. The disclosures of both applications referencedabove are incorporated herein by reference.

BACKGROUND

1. Field

The disclosure is generally related to techniques for mapping deviceaddresses to physical memory addresses.

2. Related Art

Information technology (IT) systems frequently include one or moreperipheral component interconnect (PCI) devices, e.g., PCI-expressdevices. Typical PCI devices are external peripheral devices, e.g.,external storage devices, network devices, sound devices, etc. PCIdevices access physical memory, usually implemented as random accessmemory (RAM), of an associated IT system using direct memory access(DMA), which provides an efficient way for accessing the memory. Themain storage is administered by an operating system (OS) and explicitlyprovided to be used by the PCI devices.

In order to prevent a PCI device from accessing physical memory that isnot assigned to the PCI device, PCI devices typically employ independentPCI addresses. An input/output memory management unit (IOMMU) may beprovided for translating PCI addresses into addresses that refer tophysical memory. An IOMMU can be implemented on each PCI device or as acentral part of an IT system. PCI addresses may be identical to theaddresses of underlying physical memory. PCI address space may beprovided as a copy of physical memory or an abstraction layer may beprovided for protecting main storage from unauthorized access.Typically, a PCI device provides internal device addresses that are usedby applications or libraries using the PCI device, such that furtheraddress translation is required.

The operation of the IOMMU in address translation involves functionalityof the operating system, which selects the physical memory to be used bythe PCI device. If a hypervisor is running on the IT system, thehypervisor may also be involved in the IOMMU functionality. An IOMMU maybe further configured to perform a plausibility check to restrict accessof a PCI device to memory areas of a physical memory that are reservedfor the PCI device. In the event a resource identifier (RID) istransmitted from a PCI device to an IOMMU to uniquely identify the PCIdevice, the IOMMU may verify that the requested PCI address is assignedto the PCI device. The IOMMU may, for example, be implemented in fieldprogrammable gate array (FPGA) or an application specific integratedcircuit (ASIC).

According to a first approach, an IOMMU may be centrally implemented inan IT system. In this case, a PCI device first performs a translation ofa device address to a PCI address and further transmits a request toaccess memory (based on the PCI address) to the IOMMU. The IOMMUtranslates (based on a translation table) the PCI address to a physicalmemory address and grants access to the physical memory. To reduce thesize of the required translation table, physical memory can be providedin blocks of a given size and a translation unit can be employed fortranslating only a part of a PCI address that identifies a respectivememory block. In this case, only the mapping for these blocks has to bedone, which reduces the size of the mapping table.

According to a second approach, an IOMMU (e.g., in the form of an FPGAor ASIC) may be fully implemented in each PCI device. Using the secondapproach, in the case of multiple PCI devices, multiple translationlayers are implemented. Typically, according to the first approach, anIOMMU only verifies if a PCI device is allowed to access requestedmemory and the PCI device provides PCI addresses to directly addressphysical memory. An access to physical memory that is not assigned to aPCI device is detected by an IOMMU, at which point a system hasdeactivated the entire PCI device. A PCI device may implement a key thatfacilitates a plausibility check when translating a device address intoa PCI address. The key is used internally in the PCI device todistinguish memory areas of different areas of user memory space of thePCI device.

As previously mentioned, a translation unit can be implemented in thePCI device to reduce a size of a mapping table. For example, thetranslation of the device address to the PCI address can be accomplishedby taking a part of the device address, e.g. the upper 52-bits, as abasis for the PCI address in combination with a table driven scheme. Thephysical memory address can be formed by taking the PCI address andadding a fixed offset for reading and/or writing data.

A disadvantage of the first and second approaches is that addressingerrors are handled centrally on the system, which usually results indeactivation of the entire PCI device in the case of an error. Forexample, an error can occur when a PCI address does not belong to a PCIdevice. Furthermore, the implementation of the IOMMU and the translationlayer is resource consuming, especially if the PCI device is implementedby using FPGAs for the implementation of the IOMMU and the fulltranslation layer is implemented on the PCI device. Moreover,performance of the system is reduced as the translation scheme is rathercomplicated and not very efficient.

In conventional IT systems, usually both the first and second approachesare combined which results in double consumption of resources andfurther reduces the performance of the IT systems due to doubletranslation. Accordingly, other applications running on an FPGA arelimited to remaining resources, e.g., on-chip memory of the FPGA.

SUMMARY

A data processing system includes a main storage, an input/output memorymanagement unit (IOMMU) coupled to the main storage, a peripheralcomponent interconnect (PCI) device coupled to the IOMMU, and a mapper.The system is configured to allocate an amount of physical memory in themain storage and the IOMMU is configured to provide access to the mainstorage and to map a PCI address from the PCI device to a physicalmemory address within the main storage. The mapper is configured toperform a mapping between the allocated amount of physical memory of themain storage and a contiguous PCI address space. The IOMMU is furtherconfigured to translate PCI addresses of the contiguous PCI addressspace to the physical memory address within the main storage.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notintended to be limited by the accompanying figures, in which likereferences indicate similar elements. Elements in the figures areillustrated for simplicity and clarity and have not necessarily beendrawn to scale.

FIG. 1 shows a schematic overview of an information technology (IT)system (data processing system) that includes a main storage, aninput/output memory management unit (IOMMU), and a peripheral componentinterconnect (PCI) device.

FIG. 2 shows an overview of a sparse memory allocation scheme for PCIaddress space.

FIG. 3 shows an overview of a contiguous memory allocation scheme forPCI address space.

DETAILED DESCRIPTION

As will be appreciated by one of ordinary skill in the art, the presentinvention may be embodied as a method, system, device, or computerprogram product. Accordingly, the present invention may take the form ofan embodiment including hardware, an embodiment including software(including firmware, resident software, microcode, etc.), or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a circuit, module, or system. Thepresent invention may, for example, take the form of a computer programproduct on a computer-usable storage medium having computer-usableprogram code, e.g., in the form of one or more design files, embodied inthe medium.

Any suitable computer-usable or computer-readable storage medium may beutilized. The computer-usable or computer-readable storage medium maybe, for example, but is not limited to, an electronic, magnetic,optical, electromagnetic, infrared, or semiconductor system, apparatus,or device. More specific examples (a non-exhaustive list) of thecomputer-readable storage medium include: a portable computer diskette,a hard disk, a random access memory (RAM), a read-only memory (ROM), anerasable programmable read-only memory (EPROM) or flash memory, aportable compact disc read-only memory (CD-ROM), an optical storagedevice, or a magnetic storage device. As used herein, the term “coupled”includes a direct electrical connection between elements or blocks andan indirect electrical connection between elements or blocks achievedusing one or more intervening elements or blocks.

According to the present disclosure, an IT system that includes a PCIdevice is disclosed that facilitates improved error handling whenaccessing physical memory by PCI devices. In general, the disclosed ITsystems consume fewer resources than conventional IT systems and exhibitgood performance when a PCI device is accessing physical memory.According to one or more embodiments, a system includes a main storage,an IOMMU, and a PCI device. The system is configured to allocate anamount of physical memory in the main storage, and the IOMMU isconfigured to provide access to the main storage and to map a PCIaddress from the PCI device to a physical memory address of the mainstorage.

The system also includes a mapper for mapping between the allocatedamount of memory of the main storage and a contiguous PCI address space.In one or more embodiments, the IOMMU is further configured to translatePCI addresses of the contiguous PCI address space to the physical memoryaddress within the main storage. Utilizing contiguous PCI address spaceresults in a simplified addressing scheme, which facilitatesimplementation of the IOMMU with fewer resources (e.g., IT systemresources and PCI device resources). The IOMMU may be implemented as anFPGA (e.g., an FPGA with memory such as SRAM, which can be accessedrapidly and is a usually a limited resource).

The mapper may be implemented by an OS of the system and/or by a driverof the PCI device. In the event a hypervisor is implemented within asystem, the hypervisor may entirely or partially implement the mapper.The mapper may be a combined implementation of the OS, the device driverand, if present, the hypervisor. A combined interaction can include:allocating a contiguous memory area of user memory space having acertain length; mapping the user memory space to a contiguous PCIaddress space of the same length; allocating an amount of physicalmemory, which is non-contiguous, corresponding to the length of thecontiguous memory area of user memory space; and generating a mappingbetween the physical memory addresses to the contiguous addresses in thePCI address space. The order of the mapping and allocation can be freelychosen.

In at least one embodiment, a system is configured to allocate thephysical memory in the main storage in memory blocks. The implementationof memory blocks reduces the size of a required translation table, suchthat resource consumption is further reduced. In this case, only anaddress part that corresponds to the identification of a memory blockhas to be translated. An implementation can be realized by a translationunit, which forms part of the IOMMU. In one or more embodiments, asystem is configured to allocate physical memory in main storage inmemory blocks of different block sizes. The block size can vary fromapplication to application requesting memory for the PCI device orwithin the memory assigned depending on a single application request forassigning memory.

Block sizes can also be unique for each PCI device and different PCIdevices may employ different block sizes. A system may be configured toapply a block size as a power of two, e.g., 4 kB block sizes. Employingpower of two block sizes are best used in a binary system and allow forthe addressing of the physical memory in an efficient way. According toat least one embodiment, the IOMMU is configured to translate the PCIaddress to the physical memory address by combining a first address partof the PCI address (that refers to the memory block of the physicalmemory address) and a second address part of the PCI address (thatrefers to a memory unit within the memory block). This allows accessingthe physical memory rapidly, because each block can be addressed bytranslation of the first address part and the remainder of the addresscan be taken directly from the PCI address to identify the memoryaddress within the memory block. That is, the memory address within theblock and the second part of the PCI address directly correspond to eachother.

According to another embodiment, a PCI device is configured tointernally use a device memory address. In this embodiment, the PCIdevice includes a mapping unit that is configured to translate thedevice memory address to the PCI address. The mapping unit provides animplementation within the PCI device that allows a two-stage mappingfrom the device address to the physical memory address. The mapping unitrepresents a second, independent stage for accessing the physical memoryand may include an error checking unit. Accordingly, errors can bealready handled within the PCI device, so that in case of error the PCIdevice will not be entirely disabled.

In one or more embodiments, a PCI device is configured to provideinternally individual memory areas to be addressed by the device memoryaddress. In this case, the mapping unit has a key assigned to eachindividual memory area and is configured only to translate the devicememory address into the PCI address when the device memory address isprovided with the key assigned to the memory area containing the devicememory address. The mapping unit in this case may be referred to as keymapping unit. The key facilitates verifying if an access to the memoryaddress indicated by the device address is authorized. In the event thatthe provided key does not match the key assigned to the respectivedevice memory address, access is not granted.

A mapping unit, in addition to restricting memory access, may implementerror handling for a PCI device and an application requesting the memoryaccess. The mapping unit may be configured to map the device memoryaddress to the PCI address by adding an offset to the device memoryaddress. In this case, translation of the device address to the PCIaddress can be readily calculated. The mapping unit may be configured toadd a key dependent offset. This facilitates adding key dependentoffsets, such that PCI address can be formed depending on used keys inan efficient manner For example, a mapping unit may be configured to mapa device memory address to a PCI address by bit-shifting a device memoryaddress according to a power of a given block size. When memory isallocated in memory blocks, bit-shifting may be performed based on theblock size, so that translation of a device address to a PCI address canbe performed efficiently. For example, a power of a given block size maydefine the number of bits to be shifted.

A PCI device driver may be configured to set up the mapping unit. As aPCI device driver is usually provided with the PCI device, the PCIdevice driver can perform PCI device setup under consideration ofparticular needs of the PCI device. In one embodiment, a mapper isconfigured to allocate separate contiguous areas of PCI memory withinthe contiguous PCI address space for application requests. The separateareas are provided within the contiguous PCI address space spaced apartfrom each other. This separate contiguous area allocation provides aso-called sparse allocation of the memory within the PCI address space.

Provisioning of unused memory areas within a PCI address spacefacilitates a dynamic memory allocation for different applications,since the amount of allocated memory can be easily modified. Forexample, when additional memory is requested by an application, thememory can be added within an unused memory area following an alreadyallocated memory area so that fragmentation of memory allocated for asingle application can be avoided. This approach simplifies the accessto the PCI address space based on the device address. The separatecontiguous areas of a PCI memory can be spaced apart with a predefineddistance, or the distance can be calculated dynamically, e.g. underconsideration of constraints for the requesting application. In general,the chosen distance is based on the amount of memory typically requestedby an application.

A PCI device may be configured to provide an IOMMU with a PCI addresstogether with a resource identifier that identifies the PCI device andis typically unique for each PCI device. The resource identifier enablesa plausibility check within an IOMMU. That is, an IOMMU can use theresource identifier to verify if a PCI device is attempting to access amemory that is assigned to the PCI device.

With reference to FIG. 1, an exemplary IT system (data processingsystem) 1 includes a main storage (memory) 2, an I/O memory mapping unit(IOMMU) 3, and a PCI device 4. Main storage 2 provides an amount ofphysical memory (usually as random access memory (RAM)) within IT system1. Main storage 2 is illustrated as storing a mapper 7, which is furtherdescribed below. Since the amount of available RAM is usually smallerthan the address space for the physical memory, parts of main storage 2can also be provided on a hard disk drive or other storage and beswapped between RAM and the hard disk drive. IOMMU 3 is provided toperform a translation of a PCI address to a physical memory address foraccessing main storage 2. IOMMU 3 may, for example, be implemented in anFPGA or an ASIC.

IOMMU 3 includes a translation unit 5 for translating a PCI address fromPCI address space 10 (see FIGS. 2 and 3) to a physical memory addressbased on memory blocks of a given size (e.g., 4 kB). PCI device 4 can beany kind of logical and/or physical device known in the art. PCI device4 can be used by any kind of resources (e.g., by libraries orapplications) of IT system 1. The applications and/or libraries can rundirectly on an operating system of IT system 1 or can run within ahypervisor within a virtual environment. In one or more embodiments, PCIdevice 4 includes a key mapping unit 6 that performs a mapping of deviceaddresses (used internally by PCI device 4) to PCI addresses foraccessing physical memory via IOMMU 3.

By a way of example, the processes implemented in IT system 1 aredescribed based on a single application running on IT system 1. Withreference to FIG. 3, an application initiates use of PCI device 4 byissuing an application request to allocate user memory for use by theapplication with respect to PCI device 4. A device driver (notexplicitly shown) of PCI device 4 receives the application request andallocates a contiguous area of user space 11 with a given lengthaccording to the application request. A corresponding amount of memoryis then allocated within a contiguous PCI address space 10 by the devicedriver. The allocated amount of PCI memory corresponds to the allocatedmemory of user space 11.

The device driver further sets up key mapping unit 6 and assigns a keyto the memory allocated due to the application request. The key is alsotransmitted to the application for accessing the allocated memory. Thedevice driver further initiates the operating system to allocate therequired amount of physical memory. The physical memory of main storage2 is allocated in memory blocks of size (e.g., 4 kB), which is usuallynot contiguous since main storage 2 is shared by all components of ITsystem 1. In one or more embodiments, an operating system includes amapper (not explicitly shown in the figures), which provided a mappingof the non-contiguous physical memory to contiguous addresses in PCIaddress space 10.

The device driver selects addresses within the area assigned by theoperating system and sets up translation unit 5 according to theprovided mapping. Application access to main storage 2 is performedusing the device address and the assigned key. In one or moreembodiments, key mapping unit 6 verifies if the device addresscorresponds to the key to determine whether the application isauthorized to execute the requested memory access. When a mismatchbetween the provided key and the key stored in key mapping unit 6occurs, the access to the memory is rejected and the translation is notperformed. In this case, a feedback message is provided to theapplication so that error handling can be initiated.

In the event the keys match, it is verified whether the provided deviceaddress lies inside the allocated amount of memory for the application.Since user space 11 is contiguous, the verification includes a check ofwhether the device address is bigger than the length of the requestedmemory. As previously mentioned, the physical memory may be allocated inblocks of 4 kB, which corresponds to a number of 2¹² memory cells orbytes. In one or more embodiments, a length L of user space 11 refers toa value that is based on a power of two, e.g., L=2^(m). In this case,verification includes checking whether the device address is bigger than2^(m+12), in which case the translation is rejected.

Next, key mapping unit 6 calculates the PCI address based on the deviceaddress. The calculation may include taking the device address andadding an offset (e.g., a key dependent offset) and performing abit-shift (e.g., a key dependent bit-shift). For example, thecalculation may be represented as PCI address=device address+offset(key)<<12. The above calculations are all based on the key, which hasbeen assigned to the allocated user memory of user space 11.

Key mapping unit 6 may employ a data structure that includes all itemsrequired to perform a calculation. For example, the data structure maybe an array that includes all entries for the different keys (with a keyprovided by an application being used as selector to access differententries in the data structure). For example, key mapping unit 6 may beimplemented within an FPGA with entries of the data structure beingstored in SRAM of the FPGA to allows relatively fast access. In theevent that available SRAM of the FPGA is not sufficient for all entriesof the data structure, various known update mechanisms may be used forswapping memory from the SRAM to main storage 2.

In one or more embodiments, after calculating the PCI address, PCIdevice 4 transmits the PCI address together with a resource identifier,which is assigned to PCI device 4, to IOMMU 3. IOMMU 3 performs averification of the resource identifier so that PCI device 4 can onlyaccess physical memory which has been assigned to PCI device 4.Furthermore, translation unit 5 performs a translation of the PCIaddress under consideration of the block size of allocated physicalmemory. Accordingly, translation unit 5 first takes an upper addresspart of the PCI address and performs a mapping of the upper address partto the respective memory block within main storage 2. The remaining partof the PCI address refers to the address of the memory to be accessedwithin an already identified memory block and can therefore be useddirectly for accessing the respective memory unit within the memoryblock.

When additional applications or libraries want to use PCI device 4,additional memory is required. As shown in FIG. 2, multiple user spaces11 are allocated within PCI address space 10. FIG. 2 illustrates aso-called sparse allocation of user space 11. According to this sparseallocation, multiple user spaces 11 are allocated within PCI addressspace 10, with different user spaces 11 being spaced apart from eachother. Accordingly, when an application requires further memory, thememory can be appended immediately at the end of an already allocateduser space 11 to reduce or avoid fragmentation. The memory addresswithin the PCI address space is calculated by combining an upper addresspart, denoted “key” in FIG. 2, which is characteristic for a particularuser space 11, and a lower address part, denoted “address” in FIG. 2,which corresponds to the device address. Accordingly, the applicationwill not be aware of the sparse allocation of its associated allocateduser space 11 within PCI address space 10.

In another embodiment, sparse allocation of user memory may be omitted,which results in a memory usage of PCI address space 10 as shown in FIG.3. As above, an application will not be aware of the allocation of itsallocated user space 11 within PCI address space 10. Addressing may beaccomplished as described above since the placement of user space 11 istransparent.

In another embodiment, physical memory is allocated directly and mappedto PCI address space. Accordingly, translation unit 5 and key mappingunit 6 are implemented without the handling of memory blocks. In thiscase, translation unit 5 performs direct translation of the entire PCIaddress to the physical memory address to be accessed. Moreover, keymapping unit 6 performs the check of the device address by merelycomparing whether the device address is bigger than the size ofallocated user space 11. In the event the device address is bigger thanthe size of allocated user space 11, a translation of the device addressis rejected. Additionally, the calculation of the PCI address based onthe device address is performed by merely adding the offset to thedevice address.

Accordingly, a data processing system has been disclosed herein thatadvantageously utilizes contiguous PCI address space to facilitate asimplified addressing scheme.

The flowchart and block diagrams in the figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an,” and ^(the) are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” (and similar terms, such as includes, including,has, having, etc.) are open-ended when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below, if any, areintended to include any structure, material, or act for performing thefunction in combination with other claimed elements as specificallyclaimed. The description of the present invention has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the invention in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the invention.The embodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

Having thus described the invention of the present application in detailand by reference to preferred embodiments thereof, it will be apparentthat modifications and variations are possible without departing fromthe scope of the invention defined in the appended claims.

What is claimed is:
 1. A data processing system, comprising: a mainstorage; an input/output memory management unit (IOMMU) coupled to themain storage; a peripheral component interconnect (PCI) device coupledto the IOMMU; and a mapper configured to perform a mapping between anallocated amount of physical memory of the main storage and a contiguousPCI address space, wherein the IOMMU is further configured to translatePCI addresses of the contiguous PCI address space to the physical memoryaddress within the main storage.
 2. The data processing system of claim1, wherein the system is configured to allocate an amount of physicalmemory in the main storage and the IOMMU is configured to provide accessto the main storage and to map a PCI address from the PCI device to aphysical memory address within the main storage
 3. The data processingsystem of claim 1, wherein the mapper is included within an operatingsystem of the data processing system or a PCI device driver associatedwith the PCI device.
 4. The data processing system of claim 1, whereinthe data processing system is configured to allocate the physical memoryin the main storage in memory blocks.
 5. The data processing system ofclaim 4, wherein the memory blocks have different block sizes.
 6. Thedata processing system of claim 1, wherein the data processing system isconfigured to apply a block size with a power of two.
 7. The dataprocessing system of claim 4, wherein the block size is 4 kB.
 8. Thedata processing system of claim 4, wherein the IOMMU is configured totranslate the PCI address to the physical memory address by combining afirst address part of the PCI address referring to a memory block of thephysical memory address and a second address part of the PCI addressreferring to a memory unit within the memory block.
 9. The dataprocessing system of claim 1, wherein the PCI device is configured tointernally use a device memory address and includes a mapping unit thatis configured to translate the device memory address to the PCI address.10. The data processing system of claim 9, wherein the PCI device isconfigured to provide internal individual memory areas to be addressedby the device memory address and the mapping unit has a key assigned toeach individual memory area and is configured only to translate thedevice memory address into the PCI address if the device memory addressis provided with the key assigned to the memory area that includes thedevice memory address.
 11. The data processing system of claim 10,wherein the mapping unit is configured to translate the device memoryaddress to the PCI address by adding an offset to the device memoryaddress, wherein the offset depends on the key.
 12. The data processingsystem of claim 11, wherein the mapping unit is configured to map thedevice memory address to the PCI address under application ofbit-shifting of the device memory address according to a power of agiven block size.
 13. The data processing system of claim 9, wherein aPCI device driver associated with the PCI device is configured to setupthe mapping unit.
 14. The data processing system of claim 1, wherein themapper is configured to allocate separate contiguous areas of PCI memorywithin the contiguous PCI address space for application requests, andwherein the separate areas are provided within the contiguous PCIaddress space spaced apart from each other.
 15. The data processingsystem of claim 1, wherein the PCI device is configured to provide thePCI address to the IOMMU together with a resource identifier identifyingthe PCI device.
 16. A data processing system, comprising: aninput/output memory management unit (IOMMU) coupled to a main storage; aperipheral component interconnect (PCI) device coupled to the IOMMU,wherein the system is configured to allocate an amount of physicalmemory in the main storage and the IOMMU is configured to provide accessto the main storage and to map a PCI address from the PCI device to aphysical memory address within the main storage; and a mapper configuredto perform a mapping between the allocated amount of physical memory ofthe main storage and a contiguous PCI address space, wherein the mapperis configured to allocate separate contiguous areas of PCI memory withinthe contiguous PCI address space for application requests, and whereinthe IOMMU is further configured to translate PCI addresses of thecontiguous PCI address space to the physical memory address within themain storage.
 17. The data processing system of claim 16, wherein thePCI device is configured to internally use a device memory address andincludes a mapping unit that is configured to translate the devicememory address to the PCI address.
 18. The data processing system ofclaim 17, wherein the PCI device is configured to provide internalindividual memory areas to be addressed by the device memory address andthe mapping unit has a key assigned to each individual memory area andis configured only to translate the device memory address into the PCIaddress if the device memory address is provided with the key assignedto the memory area that includes the device memory address.
 19. A methodof accessing physical memory, comprising: mapping, using an input/outputmemory management unit (IOMMU), a peripheral component interconnect(PCI) address from a PCI device to a physical memory address within mainstorage; mapping, using a mapper, between an allocated amount ofphysical memory of the main storage and a contiguous PCI address space;and translating, using the IOMMU, PCI addresses of the contiguous PCIaddress space to a physical memory address within the main storage. 20.The method of claim 19, wherein the PCI device is configured tointernally use a device memory address and the method further comprises:translating, using a mapping unit of the PCI device, the device memoryaddress to the PCI address.